Decoded: NN-PARS, simulating a circuit with neural networks instead of lookup tables

Before you start

Open only what you need; each one is a short refresher.

1. The problem: accurate simulation is slow (paper §I)

SPICE simulators are the accurate reference for analysing a circuit, but they are very slow for circuits with billions of transistors, so faster simulators use abstraction models built on lookup tables (LUTs) and closed-form expressions. Voltage-based models (such as the nonlinear delay model) store delay, noise or power in tables; the paper notes they grow less accurate at capturing signal integrity and short-channel effects as technologies scale down. Current-based models, the current source models (CSM), represent each cell with voltage-dependent components and can produce realistic output waveforms for arbitrary inputs. Their main drawback, the paper says, is the high latency of the memory queries.

NN-PARS replaces each CSM table query with a small neural network evaluated on GPU cores, and adds an event-driven scheduler that simulates many gates of the circuit in parallel. The authors suggest the approach could help other lookup-table-based simulators, but this paper develops and evaluates it with CSM. The paper's headline results, each with its own baseline: over two orders of magnitude less simulation time than the CSM lookup-table method on large circuits, and a waveform error below 2 % against HSPICE on a full adder. The paper calculates GPU latencies from its analytical equations (section 9); it does not describe an instrumented GPU timing procedure.

2. What a current source model stores (paper §II)

A CSM describes each cell by voltage-dependent current sources plus input, Miller and output capacitances. The Miller capacitance couples the input and output nodes; the figure groups the component functions that a simplified voltage update needs. For an inverter these components depend only on the input voltage V_I and the output voltage V_O; for a cell with several inputs they also depend on the other inputs and on internal nodes. Because a table needs an axis for every voltage variable, the paper notes that the size of CSM lookup tables grows exponentially with the number of variables.

3. Why a table query is slow (paper §II, Tables I and II)

Following CSM-NN [18], the paper states that high-dimensional CSM tables only fit in DRAM, while low-dimensional voltage-based tables fit in L1 caches. On its example CPU, a 24-core Intel Xeon E7-8894 v4 (Table I), a DRAM access takes about 250 cycles against 4–5 cycles for L1, and the 24 cores share only 4 memory channels. A GPU has two levels of parallel units: streaming multiprocessors (SMs), each with many cores (stream processors) that have their own arithmetic units and register files. The paper's example GPU is an NVIDIA Tesla V100 (Table II: 80 SMs, 64 single-precision cores per SM). The paper's Fig. 1 shows peak GPU floating-point throughput pulling away from CPUs between 2007 and 2018.

Earlier work, CSM-NN [18], already replaced table queries for simple gates with neural-network calculations, but did not show how to scale this to circuit simulation, especially on GPUs. NN-PARS builds on that work by organizing concurrent circuit simulation and scheduling the gates on a GPU.

4. One network per cell, judged by its waveform (paper §III-A)

NN-PARS uses the same characterisation as the CSM lookup-table method and the same training flow as CSM-NN: characterisation collects component values at known voltages, a network learns to approximate each voltage-dependent component function, and the simulator uses its predictions to advance the node voltages over successive intervals. The network does not predict a whole waveform; the paper does not say whether the current and the capacitances use separate networks or one network with several outputs. Every cell in the library gets its own network with a single hidden layer. The paper stresses that accuracy must be judged on the output waveform, not only on one measurement such as delay, and defines the expected waveform similarity E_sim (eq. 1): the time-average of |V_SPICE − V_NN-PARS| over the simulated time T, divided by the supply voltage V_DD. Despite its name, E_sim is an error: zero means identical waveforms, and smaller is better. The figure marks each waveform's 50 % crossing, the time it reaches half the supply voltage; matching that one time does not ensure that the rest of the waveform matches.

E_sim also chooses each network's size: the smallest hidden layer that passes a set accuracy threshold when driven with noisy inputs is kept (section 9 gives the values).

5. How many cycles one network takes (paper §III-B)

Here D counts the numerical voltage inputs to a network, not the Boolean input pins of a gate, and H counts hidden neurons. A reduction tree adds independent pairs at the same time, then repeats with their partial sums. A GPU core performs one multiplication and one addition per cycle. With D inputs and H hidden neurons, the first layer has D × H independent multiplications, so D × H cores compute them in a single cycle. In the paper's latency model, each hidden neuron's terms are reduced by a tree in ⌈log₂(D+1)⌉ cycles; the paper notes that the first tree cycle needs only (D+1)/2 cores per neuron, so the initially allocated D × H cores are reused for the additions. The output layer follows the same pattern, which gives the paper's eq. 2: latency = 1 + ⌈log₂(D+1)⌉ + 1 + ⌈log₂(H+1)⌉ cycles on D × H cores. Because the trained weights are fixed, they can sit in the cores' register files, so the evaluation needs no table retrieval from memory. Eq. 2 is an analytical count of the multiplications and additions; it is not a complete GPU execution trace, and the extra term in D+1 and H+1 is the lesson's interpretation (for example a bias), not something the paper explains.

6. Why every gate of an interval can run at once (paper §III-C)

Here ΔV_I is an input-voltage change over one simulation interval dT; in the voltage-based comparison, slew means a signal's transition duration. CSM simulation computes waveforms in a series of short time intervals dT. If the voltages and input slews of all gates are known in interval T_i, each gate's voltage change for the next interval can be computed, and the change of a driver's output voltage in one interval becomes the input-voltage change of its load in the next. Within one interval the gates therefore do not depend on each other and can be simulated in parallel. Voltage-based simulation instead computes a gate's delay and output slew from its input slew, which is its driver's output slew, so gates on different levels of the circuit cannot be simulated in parallel. The figure's current and next banks illustrate this dependency rule; they are not the paper's storage scheme, integration formula or choice of dT.

7. Placing models on the GPU (paper §III-D)

A model instance is a reusable copy of one cell type's trained network, not a particular gate and not a GPU multiprocessor. The paper walks through the flow on the ISCAS85 benchmark circuit C7552 with the V100 of Table II, limiting the library to INV, NAND2 and NOR2. NN-PARS first counts the gates of each cell: 2625 NAND2, 799 INV and 401 NOR2. Based on the ratio of these counts it dedicates GPU cores to network models of each cell; Fig. 2 shows 52 NAND2, 20 INV and 8 NOR2 models (for FinFET 7 nm), so 80 gates can be simulated in parallel per round, and the paper states that one time interval of C7552 takes the GPU 3825/80 iterations, a workload-to-capacity ratio of about 47.8. The 52/20/8 placement is the paper's example: it does not give a formula that derives this exact allocation from the gate ratios, and with fixed per-type slots the integer number of rounds depends on the longest queue, so 3825/80 alone does not determine it.

8. Skipping gates that are not changing (paper §III-D)

Choosing gates at random for each round works, but the paper notes it may not be optimal: in a large circuit many cells need no simulation in an interval because none of their node voltages changed in the previous one. The event-driven scheduler keeps an active set: cells whose voltages changed beyond a threshold are added and simulated in the next time frame, and cells with no change on any of their voltage nodes are removed. A skipped cell can be queued because a driver changed one of its input nodes; detecting that change is not the same as evaluating the cell. The paper gives no threshold value and no error bound for skipping; the figure's numbers are illustrative.

9. Setup and choosing each network's size (paper §IV, §IV-A, §IV-B)

The authors implemented the simulator and its flow in Python, with networks built and trained in Scikit-learn. The CPU of Table I runs the CSM lookup-table baseline and the GPU of Table II runs NN-PARS; the two platforms were chosen as comparable in cost (about 8,000 USD) and production year (2017). The paper calculates the GPU resource requirements and latencies from its analytical equations (section 5); it does not describe an instrumented GPU timing procedure. The implementation supports configurable cell characterisation, and the circuits tested are combinational netlists. Experiments use the Predictive Technology Model 16 nm MOSFET and 7 nm FinFET devices, each in a high-performance (HP) and a low-standby-power (LP) variant.

Characterisation gives 500 samples per gate, split at random into 90 % training and 10 % test data. Because the output current spans picoamperes to microamperes, the networks are trained on log I_O, and the solver normalises the data for faster convergence and numerical stability. Hidden-layer sizes from 5 to 40 were each trained and tested with noisy input signals, and the smallest size with E_sim < 1 % was kept (Table III). The held-out 10 % checks the fitted function at sample points; the noisy-input test checks simulated waveforms. The selected INV widths range from 8 to 10 neurons and the NAND2 and NOR2 widths from 17 to 21 across the four variants; the figure shows each reported choice.

10. What the paper reports: waveform accuracy and calculated speed-up (paper §IV-C, Tables IV and V)

A full adder adds three one-bit inputs and returns a sum bit S and a carry bit C_out. The full adder (inputs A, B and C_in, outputs S and C_out; Fig. 3) is simulated in all four technology variants. Its output waveforms from SPICE, the CSM lookup-table method and NN-PARS are compared in Fig. 4, and E_sim against HSPICE stays under 2 % (Table IV). The paper reports a 30.4× speed-up for the full adder in every variant, explaining that all of its gates fit on the GPU at once; because so few gates do not show the full gain, it also reports speed-ups for ISCAS85 circuits with hundreds to thousands of gates (Table V). Speed-up is the CSM lookup-table simulation time on the CPU divided by the NN-PARS time, with the GPU latencies calculated from the paper's equations. The earlier waveform drawing explained the metric with invented curves; the figure below summarises the reported numbers rather than reproducing Fig. 4. The full-adder waveform errors range from 1.27 % to 1.81 %, and Table V reports speed-ups from 81× to 134× for the larger benchmarks.

What the paper concludes (paper §V)

The paper's goal was to remove the accuracy and latency problems of simulators that depend heavily on memory queries. NN-PARS replaces the long table queries of current source models with small, parallel neural-network computations and adds an event-driven scheduler that runs the simulation of many cells concurrently. Across MOSFET and FinFET predictive technology models it reports calculated speed-ups of up to 134× over the CPU CSM lookup-table baseline on large circuits, while the full-adder waveform comparison has an error under 2 % against HSPICE. The authors expect the method to help the analysis and optimisation of large designs such as systems-on-chip.

Sources and credits

1. Paper — Mohammad Saeed Abrishami, Hao Ge, Justin F. Calderon, Massoud Pedram and Shahin Nazarian. NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework. 21st International Symposium on Quality Electronic Design (ISQED 2020), pp. 452–456, 2020. arXiv:2002.05292
2. Paper — Abrishami, Ge, Calderon, Pedram and Nazarian, ISQED 2020, pp. 452–456 (DOI 10.1109/ISQED48828.2020.9137047); text read from the arXiv version linked above.
3. Method it builds on — CSM-NN (Abrishami, Pedram and Nazarian, ICCD 2019), which the paper cites as [18]: neural networks in place of current-source-model table queries for single gates. The paper names Scikit-learn as the package its networks were implemented and trained with.
4. Figures — All figures on this page are original drawings written for this lesson from the paper's text, with small illustrative sizes (a network with 3 inputs and 4 hidden neurons, three-gate and six-gate netlists, five time intervals) where the paper's real sizes would not fit on screen; illustrative values are labelled on each drawing. Nothing is reproduced from the paper's figures; numbers quoted from its tables are cited to the table.

The explanations and interactive drawings are original interpretations of the cited research. Rights in the papers remain with their respective rightsholders; citation does not imply endorsement.

© 2026 Justin Calderon. All rights reserved. Applies to original lesson material, subject to rights provided by law. See Sources and rights or rights.txt. Request a correction or removal.